1. Field of the Invention
The present invention relates to an interface circuit and, particularly, to an interface circuit that changes a signal level used for a high-speed A/D converter or the like, which is particularly used in a wireless communication system.
2. Description of Related Art
In a wireless communication system such as Global Positioning System (GPS) receiver, an internal system is largely classified into a high-frequency analog signal processor and a low-frequency baseband digital signal processor. The high-frequency analog signal processor uses a low amplitude signal at Emitter Coupled Logic (ECL) level, for example, in order to perform high-speed signal processing. On the other hand, the low-frequency baseband digital signal processor performs signal processing at high amplitude Complimentary Metal Oxide Semiconductor (CMOS) level. Since there are two signal levels in one system, a wireless communication system needs to have an interface circuit for converting signal levels in order to process different levels of signals. Further, a capacitive load such as a gate of a CMOS transistor is connected to the subsequent stage of the interface circuit. In order to achieve the high-speed signal processing, the interface circuit needs to have such a current output capacity as to charge the capacitive load quickly.
To meet these needs, interface circuits often use Bipolar-Complimentary Metal Oxide Semiconductor (BiCMOS) process. An interface circuit that uses the BiCMOS process is disclosed in Japanese Unexamined Patent Application Publication No. 06-204844. Recently, there are increasing demands on GPS receivers or the like for size reduction, cost reduction, sensitivity increase and power consumption reduction. To meet the demands for size reduction, an interface circuit tends to be incorporated into a high-frequency integrated circuit (IC) that processes a high-frequency analog signal. To meet the cost reduction and sensitivity increase, a manufacturing process of a high-frequency IC employs a bipolar process. Thus, it is required to configure an interface circuit with low power consumption by using the bipolar process.
FIG. 7 shows a circuit diagram of a normal conventional interface circuit in a bipolar process. The interface circuit 700 of FIG. 7 is capable of converting an ECL level signal into a CMOS level signal. However, the conventional interface circuit needs to set the current to charge a capacitance load with the current to be supplied to an input stage. It is thus possible to supply a large current to the input stage, which causes an increase in current consumption of the entire circuit. Further, in the conventional interface circuit, a PNP transistor and an NPN transistor are connected between a power supply VCC and a ground GND and a signal is output from a node between the two transistors. An output signal has an amplitude that substantially ranges from a power supply voltage VCC to a ground voltage GND.
FIG. 8 are graphs of the base voltage waveform of the PNP transistor Q714, the collector current waveform of the PNP transistor Q714, the current waveform of the entire circuit and the voltage waveform at the output OUT in the interface circuit 700. FIG. 8 shows that a through current flows through the collector of the PNP transistor Q714 at the falling edges of an output signal in the conventional interface circuit 700. The through current flows because the NPN transistor Q718 switches from the shutoff state to the saturated state before the PNP transistor Q714 switches from the saturated state to the complete shutoff state. The PNP transistor Q714 switches between the saturated state and the shutoff state depending on its base voltage. The base voltage of the PNP transistor Q714 is determined by the current flowing through the PNP transistor Q713. However, the current flowing through the PNP transistor Q713 changes from a predetermined current amount to zero when the PNP transistor Q714 switches from the saturated state to the shutoff state. Since no current flows to the PNP transistor Q713, the base voltage of the PNP transistor Q714 becomes unstable. Therefore, the PNP transistor Q714 cannot switch from the saturated state to the shutoff state immediately. As a result, the conventional interface circuit 700 has a problem that a through current flows in when the PNP transistor Q714 switches from the saturated state to the shutoff state, which hinders the achievement of higher signal level conversion speed.